Rf quadrature mixing digital-to-analog conversion

ABSTRACT

A double-balanced radio-frequency (RF) mixing digital-to-analog converter (DAC) apparatus includes a load network, a first set of resistive DAC driver circuits and a first mixing core. The first mixing core can receive first RF input signals from the first set of resistive DAC driver circuits and can provide a first mixed signal to the load network. The first mixing core includes a first input differential pair coupled to two first cross-coupled differential pairs. The first input differential pair can receive first RF input signals at respective first input nodes. Each of the two first cross-coupled differential pairs can receive first positive and negative local oscillator (LO) signals at corresponding first input nodes. The first mixing core can mix the first RF input signals with the first positive and negative LO signals.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 16/609,630,filed on Oct. 30, 2019, which is a national stage entry of ApplicationNo. PCT/US2018/030532, which claims the benefit of U.S. ProvisionalApplication No. 62/500,413, filed on May 2, 2017, the entirety of eachof which is incorporated herein by reference for all purposes.

TECHNICAL FIELD

The present description relates in general to radio frequency (RF)systems, and more particularly to, for example, without limitation, RFquadrature mixing digital-to-analog conversion.

BACKGROUND

Digital-to-analog converter (DAC) circuits are commonly used to convertdigital signals to analog signals. Example applications of DAC circuitsare in communication devices and systems. For instance, almost allcommunication devices such as hand-held communication devices includingsmart phones, tablets, phablets, and other communication devices employone or more DAC circuits. DAC circuits are characterized by propertiessuch as resolution, accuracy, and maximum sampling frequency, and can beimplemented in integrated circuits based on a number of differentarchitectures.

The description provided in the background section should not be assumedto be prior art merely because it is mentioned in or associated with thebackground section. The background section may include information thatdescribes one or more aspects of the subject technology.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating an example of asingle-balanced RF mixing digital-to-analog converter (DAC)configuration.

FIGS. 2A-2B are schematic diagrams illustrating examples of adouble-balanced RF mixing DAC configuration.

FIG. 3 illustrates an example of a quadrature mixer.

FIGS. 4A through 4C illustrate an example of a local oscillator(LO)-tone signal cancellation scheme.

FIG. 5 is a block diagram illustrating an example implementation of aquadrature RF mixing DAC configuration.

FIG. 6 is a schematic diagram illustrating an example of a quadrature RFmixing DAC circuit.

FIG. 7 is a schematic diagram illustrating an example of a folded RFmixing double-balanced DAC circuit.

FIG. 8 is a schematic diagram illustrating an example of a foldedquadrature RF mixing DAC circuit.

FIG. 9 is a schematic diagram illustrating an example of adouble-balanced RF mixing DAC circuit.

FIG. 10 is a schematic diagram illustrating an example implementation ofthe quadrature RF mixing DAC circuit . . .

FIG. 11 is a schematic diagram illustrating an example of a basisinterleaved RF mixing current steering DAC driver circuit.

FIG. 12 is a schematic diagram illustrating an example of an RFquadrature RF mixing interleaved current steering DAC circuit.

FIG. 13 is a schematic diagram illustrating an example of a modified RFquadrature mixing interleaved current steering DAC circuit.

FIG. 14 is a flow diagram illustrating an example method of providing asingle-balanced RF mixing DAC circuit.

In one or more implementations, not all of the depicted components ineach figure may be required, and one or more implementations may includeadditional components not shown in a figure. Variations in thearrangement and type of the components may be made without departingfrom the scope of the subject disclosure. Additional components,different components, or fewer components may be utilized within thescope of the subject disclosure.

DETAILED DESCRIPTION

The detailed description set forth below is intended as a description ofvarious implementations and is not intended to represent the onlyimplementations in which the subject technology may be practiced. Asthose skilled in the art would realize, the described implementationsmay be modified in various ways, all without departing from the scope ofthe present disclosure. Accordingly, the drawings and description are tobe regarded as illustrative in nature and not restrictive.

In one or more aspects, an RF mixing DAC is provided. The RF mixing DACof the subject technology integrates the function of the mixer and theDAC into a single circuit. The DAC can be a resistive DAC or acurrent-steering DAC, and the mixer can be a single-balanced or adouble-balanced RF mixer. The subject disclosure introduces a newarchitecture for integrating the functions of a mixer and adigital-to-analog converter together to form an up-conversiontransmitting device for an RF system. In the disclosed architecture, aquadrature mixing approach is used for image rejection and LOcancellation. The quadrature approach can also be adapted for a currentsteering architecture and an interleaved architecture. The existingapproaches do not incorporate any quadrature (i.e. I-Q phases) orinterleaved architecture. In addition, the exiting designs typically usea current steering DAC approach and do not utilize the resistive DACapproach of the subject technology.

The subject technology further allows adapting quadrature RF mixing DACusing a current-steering approach in a DAC architecture that can includea common-mode logic-based (CML-based) or folded architecture. In someaspects, a hybrid DAC, combining both a current steering and a seriesself-terminated (SST) approach can be used.

FIG. 1 is a schematic diagram illustrating an example of asingle-balanced RF mixing digital-to-analog converter (DAC)configuration. The single-balanced RF mixing DAC circuit 100 shown inFIG. 1 includes a series self-terminated (SST) driver resistive DAC(RDAC) circuit 110 and a single-balanced RF mixer 120 (hereinafter“mixer 120”). An exploded view 112 shows an example implementation ofthe resistive DAC circuit 110. The resistive DAC circuit 110, as shownin the exploded view 112 is a voltage mode DAC driver realized usingresistors and inverters. Each input branch of the resistive DAC caninclude two inverters 114 and a resistor 116 and receives a respectivedigital signal (e.g., D1, D2 . . . DN) that is based on a bit of thedigital input signal. In an aspect, the resistive DAC circuit 110 may beassociated with 4 bits, 16 bits, or other number of bits depending onthe application. The analog output signal of the resistive DAC circuit110 is provided to the mixer 120 coupled to the output node of theresistive DAC circuit 110. The analog output of the resistive DACcircuit 110 is coupled via a filter 102 to an RF input of the mixer 120.

The filter 102, as shown in the exploded view 104 can be a couplingcapacitor C, and in some implementations, may include bias resistors Raand Rb. The coupling capacitor C is open circuit for DC current and canblock DC currents. The bias resistors Ra and Rb couple an input node ofthe mixer 120 to the supply voltage (e.g., VDD) and the groundpotential. In the absence of the bias resistors Ra and Rb, the inputnode of the mixer 120 floats and has no fixed bias voltage. The biasresistors Ra and Rb can function as a voltage divider and provide afixed portion of the supply voltage to the input node of the mixer 120,which is isolated from any DC current flowing from the resistive DACcircuit 110 due to the DC blocking capacitor C. The bias resistors Raand Rb may also work as the termination resistors for the resistive DACcircuit 110.

The mixer 120 receives an RF signal generated (by conversion of thedigital signal) by the resistive DAC circuit 110 and mixes the RF signalwith a local oscillator (LO) applied to the mixer circuit asdifferential LO+ and LO− signals. The mixer 120 includes a switchingdifferential pair of transistors T1 and T2 (e.g., MOS such as NMOStransistors) and has a third transistor T3 coupled between common sourceof the transistor T1 and T2 and the ground potential. The RF signal isapplied to the gate of the third transistor T3 and generates acorresponding drain current that is modulated by the LO signals appliedto the gate nodes of the transistors T1 and T2 of the switchingdifferential pair. The transistors T1 and T2 of the switchingdifferential pair are coupled to a supply voltage VDD through a loadnetwork 122 formed of load resistors RL, and the intermediate frequency(IF) output is drawn from the drain nodes of the transistors T1 and T2of the switching differential pair at output nodes 124.

In one or more embodiments, a cascode circuit 125 (not shown forsimplicity) can be added between the load resistors RL and the switchingdifferential pair to provide further isolation of the output from the LOsignals. This cascode circuit 125 can prevent LO leakage to the outputnodes 124, which is ideally supposed to provide a pure IF signal. Insome implementations, a current-steering DAC can replace the resistiveDAC circuit 110. The use of the resistive DAC circuit 110, however, ismore advantageous, for ease of implementation and higher bandwidth andlinearity performance.

FIGS. 2A-2B are schematic diagrams illustrating examples of adouble-balanced RF mixing DAC configuration. The double-balanced RFmixing DAC circuit 200A (hereinafter “mixing DAC circuit 200A”) of FIG.2A is a differential configuration based on the single-balanced RFmixing DAC circuit 100 of FIG. 1. The mixing DAC circuit 200A can bethought of as a parallel combination of two single-balanced RF mixingDAC (e.g., 100 of FIG. 1) where LO− nodes of the two switchingdifferential pairs (e.g., transistor pairs T3-T4 and T5-T6) are coupledtogether, and the source nodes of the third transistors (e.g.,transistor T1 and T2) are jointly coupled to the ground potential. Thedifferential pairs T3-T4 and T5-T6 are coupled as a cross-coupleddifferential pairs 230. In the cross-coupled differential pairs 230,drain nodes of transistor T4 and T6 are coupled to a node 236 and drainnods of transistor T3 and T5 are coupled to a node 238. The node 236 and238 are connected to output nodes 224 of the mixing DAC circuit 200A.The common source nodes 232 and 234 of the cross-coupled differentialpairs 230 are connected to drain nodes of transistors T1 and T2 of aninput differential pair 220.

In one or more embodiments, a cascode circuit 225 (not shown forsimplicity) can be added between the load resistors RL and thecross-coupled differential pairs 230 to provide further isolation of theoutput from the LO signal to prevent LO leakage to the output nodes 224,which is ideally supposed to provide a pure IF signal.

The resistive load 222 is similar to the resistive load 122 of FIG. 1. Acascode circuit 225 (not shown for simplicity) can be coupled to isolatethe output nodes 224 from the LO signals (e.g., LO+ and LO−). The tworesistive DACs (RDACs) 210-1 and 210-2 are coupled to input nodes (RFnodes) of the third transistors T1 and T2 of the input differential pair220 via respective DC blocking networks 202-1 and 202-2. In someimplementations, a current-steering DAC can replace the RDACs. The useof the RDACs, however, is more advantageous, for ease of implementation,higher bandwidth, and linearity performance.

The double-balanced RF mixing DAC circuit 220B shown in FIG. 2B issimilar to the mixing DAC circuit 220A of FIG. 2A, except for theaddition of a tail current bias transistor T7. The tail current biastransistor T7 is coupled between the joint source node of the thirdtransistors T1 and T2 and the ground potential. It is understood thatthe addition of the tail current bias transistor T7 is only possible ifsufficient headroom is provided by the DC supply voltage VDD. In someimplementations, a current-steering DAC can replace the resistive DACs210-1 and 210-2. The use of the resistive DACs 210-1 and 210-2, however,is more advantageous, for ease of implementation, higher bandwidth, andlinearity performance.

FIG. 3 illustrates an example of a quadrature mixer 300. The quadraturemixer 300 of FIG. 3 includes two mixers 320-1 and 320-2 that canrespectively mix quadrature input signals, for example, an in-phase (I)signal (I=A cos (ω_(IF)t)) and a quadrature (Q) signal (Q=A sin(ω_(IF)t)) with quadrature LO signals (e.g., cos (ω_(LO)t) and sin(ω_(LO)t)) generated by the LO generator 330 to create lower band andhigher band mixing products. It is understood that the quadraturesignals have 90° phase difference that are created by a phase shiftcircuit 310. Note that the lower-band mixing product, ω_(LO)-ω_(IF), iscancelled out through appropriate phase manipulation and addition at thesummer output 340. At the end, only the higher-band mixing product,ω_(LO)+ω_(IF), remains at the output. One advantage of the quadraturemixer 300 is that the automatic cancellation of the lower side-bandmixing product negates the need for any bandpass filtering at theoutput. The subject disclosure replaces the two mixers 320-1 and 320-2of the quadrature mixer 300 with quadrature RF mixing DACs of FIG. 2A or2B.

FIGS. 4A through 4C illustrate an example of a local oscillator(LO)-tone signal cancellation scheme. In FIGS. 4A through 4C, the X-axisdenotes frequency and LO is the LO frequency. I and Q are I-phase andQ-phase of the IF frequency, respectively. The signal components 402 and404 shown in FIG. 4A are translated/mixed-up in-phase signals. The tonesignals shown 406 and 408 in FIG. 4B are translated/mixed-up quadraturesignals. The tone signals 410 and 412 shown in FIG. 4C aretranslated/mixed-up RF signals that are produced by summing the tonesignals in FIGS. 4A and 4B. In the summation, the image componentsrepresented by LO-I (e.g., 402) and LO-Q (e.g., 404) cancel out (imagerejection), whereas the signal components 404 and 408 add up to form thesummed signal 412.

FIG. 5 is a block diagram illustrating an example implementation of aquadrature RF mixing DAC configuration 500. The configuration shown inFIG. 5 is an RF mixing DAC implementation of the quadrature mixer ofFIG. 3, which uses both an I-phase and a Q-phase for image rejection andcancellation, as discussed above with respect to FIGS. 4A-through 4C.The quadrature RF mixing DAC configuration 500 includes I- andQ-sections 520-I and 520-Q, a summation circuit 530 and a bandpassfilter (BPF) 540. The I-section 520-I includes an I-DAC 522-I, alow-pass filter (LPF) 524-I and a I-mixer 526-I. The Q-section 520-Qincludes a Q-DAC 522-Q, a low-pass filter (LPF) 524-Q and a Q-mixer526-Q. The I- and Q-sections 520-I and 520-Q receive digital input I andQ signals (e.g., IF signals) from a complex digital signal source 510such as a baseband processor. The I-mixer 526-I and the Q-mixer 526-Qcan up-convert the IF signals using LO signals (e.g., I_LO and Q_LO).The output signals of the I- and Q-mixers 526-I and 526-Q are summed bythe summation circuit 530 and filtered via the BPF 540 to generate acomposite RF-DAC output signal with a frequency within a range of about80-128 GHz. 100341 FIG. 6 is a schematic diagram illustrating an exampleof a quadrature RF mixing DAC circuit 600. The quadrature RF mixing DACcircuit 600 (hereinafter “mixing DAC circuit 600”) is formed bycombining two double-balanced mixer circuits 630-I and 630-Q, which aresimilar to the double-balanced mixer circuit 200B of FIG. 2B, describedabove. The double-balanced mixer circuit 630-I is used as an I-mixer,and the double-balanced mixer circuit 630-Q is employed as a Q-mixer.The I-mixer 630-I receives I-RF signal from I-DAC 620-I and the Q-mixer630-Q receives Q-RF signal from Q-DAC 620-Q. The I-DAC 620-I includesRDACs 610-1 and RDAC 610-2 and DC-blocking circuits 602-1 and 602-2,which are similar to the RDAC 201-1 and 201-2 and the DC-blockingcircuits 202-1 and 202-2 of FIG. 2A. The Q-DAC 620-Q is similar to theI-DAC 620-I and its circuit details are not shown for simplicity. Theoutput signals of the I-mixer 630-I and the and the Q-mixer 630-Q arecoupled together to a load network 622 formed of the load resistors RL,which also performs the role of the summation circuit 530 of FIG. 5.

FIG. 7 is a schematic diagram illustrating an example of a folded RFmixing double-balanced DAC circuit 700. The folded RF mixingdouble-balanced DAC circuit 700 includes a main differential pair branch720 and a folded LO branch 730 coupled in parallel. The RF differentialsignals (RF+and RF−) are provided at the output nodes of the resistiveDACs 710-1 and 710-2 of the main differential pair branch 720, and thedifferential LO signals (LO+and LO−) are applied to gates of twocross-coupled differential pairs 732 of the folded LO branch 730. Thefolded LO branch 730 is the switching branch that includes cross-coupleddifferential pairs 732, which are coupled via the tail transistors T1and T2 to the ground potential. The gate nodes of the tail transistorsT1 and T2 are coupled to a suitable bias point. It is understood thatthe folded RF mixing double-balanced DAC circuit 700 is not a quadratureimplementation. The resistive DACs 710-1 and 710-2 are similar toresistive DACs 210-1 and 210-2 of FIG. 2-A discussed above. The outputnodes of the folded LO branch 730 are connected, at nodes 723 and 725 tosource nodes of PMOS transistors T3 and T4 of a differential pair 740.The nodes 723 and 725 are coupled via a pair of bias current sources 726to a supply voltage VDD. The load network 722 is formed of two loadresistors RL and the output signal can be derived from the output nodes724, which are the connection points of the load network 722 and drainnodes of the transistors T3 and T4 of the differential pair 740.

FIG. 8 is a schematic diagram illustrating an example of a foldedquadrature RF mixing DAC circuit 800. The folded quadrature RF mixingDAC circuit 800 includes two quadrature RF mixer branches includingdifferential pairs 840-I and 840-Q and bias current sources 826-I and826-Q and two folded quadrature LO branches 830-I and 830-Q coupled inparallel. For simplicity, only one of the two folded quadrature LObranches (830-I) coupled to nodes 823-I and 825-I is shown and the 830-Qbranch coupled to nodes 823-Q and 825-Q is shown. The differential pairs840-I and 840-Q of the quadrature RF mixer branches are similar to thedifferential pair 740 of the main differential pair branch 720 of FIG. 7coupled in parallel. The two differential pairs 840-I and 840-Q share aload network 822 that is formed of a pair of load resistors coupled tothe ground potential. The I and Q RF DACs 810-I and 810-Q provide I-RF+and I-RF+ and Q-RF− and Q-RF+ signals. The I-RF+ and Q-RF+ signals areprovided to the gate nodes of the transistors T1 and T2 of thedifferential pair 840-I, and the I-RF− and Q-RF− signals are provided tothe gate nodes of the transistors T3 and T4 of the differential pair840-Q. The folded quadrature LO branches 830-I and 830-Q (not shown forsimplicity) are similar to the folded LO branch 730 of FIG. 7. One ofthe folded quadrature LO branches (e.g., 830-I) is used as the I-mixerfor the LO signals and the other one (e.g., 830-Q, not shown) is used asthe Q-mixer for the LO signals.

FIG. 9 is a schematic diagram illustrating an example of adouble-balanced RF mixing DAC circuit 900. The double-balanced RF mixingDAC of 900 is similar to the double-balanced RF mixing DAC of FIG. 2Band is shown in FIG. 9 to indicate that the entire portion of thecircuit 950 enclosed in the broken line box can be replaced with acurrent steering DAC. In other RF mixing DACs discussed above, theresistive DACs can be similarly replaced with current steering DACs, aswill be described herein

FIG. 10 is a schematic diagram illustrating an example of a quadratureRF mixing current steering DAC circuit 1000. The quadrature RF mixingcurrent steering DAC circuit 1000 is a Current steering DACimplementation of the quadrature RF mixing DAC circuit 600 of FIG. 6,which was implemented using resistive DAC circuits 620-I and 620-Q. Inthe current steering DAC circuit 1000, current steering DACs 1010-I and1010-Q replace the resistive DAC circuits 620-I and 620-Q of FIG. 6. Thecurrent steering DACs 1010-I and 1010-Q are similar in structure andfunctionalities. For example, the current steering DACs 1010-I includesN differential pairs (e.g., formed of transistors T2 and T3) coupled viaa tail transistor T1 to the ground potential. The number N representsthe number of bits of the digital input signal. The differential pair ofthe current steering DACs 1010-I are coupled to RF inputs (e.g., RF+ andRF−) of the LO switches of a mixer core 1030-I. Similarly, thedifferential pair of the current steering DACs 1010-Q are coupled to RFinputs of the LO switches of a mixer core 1030-Q. The mixer cores 1030-Iand 1030-Q are cross-coupled differential pairs discussed above. Theoutput of the mixers cores 1010-I and 1010-Q are coupled to the loadnetwork 1022, which is similar to the load network 622 of FIG. 6.

FIG. 11 is a schematic diagram illustrating an example of a basisinterleaved RF mixing current steering DAC driver circuit 1100. Thebasis interleaved RF mixing current steering DAC driver circuit 1100includes two similar RF mixing current steering DAC driver circuits1120-1 and 1120-2, which are interleaved at their output nodes 1124-1and 1124-2. The RF mixing current steering DAC driver circuit 1120-1includes a current steering DAC 1110-1 and the RF mixing currentsteering DAC driver circuit 1120-2 includes a current steering DAC1110-2. The current steering DAC 1110-1 is similar in structure andfunctionalities to current steering DAC 1110-2 and to the currentsteering DAC driver circuit 1020-1 of FIG. 10 described above. Themixing cores of the two RF mixing current steering DAC driver circuits1120-1 and 1120-2 are similar and each is formed of first differentialpair (e.g., T1 and T2) coupled in parallel with a second differentialpair (e.g., T3 and T4). For example, the first differential pairreceives positives LO signals (I-LO) and provides first output current(e.g., Ioutp). The second differential pair receives negative LO signals(IB-LO) and provides dump currents (e.g., Idump) for the first set ofcurrent-steering DAC driver circuits when transistors of the firstdifferential pair are off. The two RF mixing current steering DAC drivercircuits 1120-1 and 1120-2 and their interleaved connections arerepresented symbolically with an equivalent circuit block 1104 shown onthe right-hand side of the FIG. 11. The equivalent circuit block 1104 isused in the following figure to represent the two RF mixing currentsteering DAC driver circuits 1120-1 (e.g., DACA) and 1120-2 (e.g., DACB)with their associated clocks (e.g., I-LO and IB-LO). Each of the DACsreceive two complementary sets of N bit digital signals. For example,the DACA receives N-bit dataAp and N-bit dataAn, and the DACB receivesN-bit dataBp and N-bit dataBn. It is noted that dataBp and dataBn arecomplements of the dataAp and dataAn.

FIG. 12 is a schematic diagram illustrating an example of an RFquadrature mixing interleaved current steering DAC circuit 1200. The RFquadrature mixing interleaved current steering DAC circuit 1200 includesRF mixing current steering DAC driver circuits 1204-I and 1204-Q, whichare interleaved and are similar to the equivalent circuit block 1104 ofFIG. 11 described above. The corresponding DACA and DACB of the RFmixing current steering DAC driver circuits 1204-I and 1204-Q aresimilarly interleaved at their connections to the load circuit 1222 thatincludes resistive loads RL that are coupled to VDD, and provide anoutput signal at output nodes 1224. The corresponding DACA and DACB ofthe RF mixing current steering DAC driver circuits 1204-I and 1204-Q areclocked by their respective I-clk (e.g., I-LO and IB-LO) and Q-clk(e.g., Q-LO and QB-LO).

FIG. 13 is a schematic diagram illustrating an example of a modified RFquadrature mixing interleaved current steering DAC circuit 1300. Themodified RF quadrature mixing interleaved current steering DAC circuit1300 is a modified version of the RF quadrature mixing interleavedcurrent steering DAC circuit 1200 of FIG. 2 with addition of T-coilnetworks 1320-I and 1320-Q and a power combiner circuit 1350. The T-coilnetworks 1320-I and 1320-Q couple output nodes of the respective I and Qequivalent circuit blocks 1304-I and 1304-B to the power combinercircuit 1350, which provides an output signal at the output nodes 1324.Each of the I and Q equivalent circuit blocks 1304-I and 1304-B aresimilar to the equivalent circuit block 1104 of FIG. 11 described above.Each of the T-coil networks 1320-I and 1320-Q include a T-coil formed ofan inductive circuit and are coupled through respective load networksformed of load resistors (RL) to VDD. In one or more implementations,the power combiner circuit 1350 can be implemented with passive elementssuch as resistors, inductor, or transmission lines.

FIG. 14 is a flow diagram illustrating an example method 1400 ofproviding a single-balanced RF mixing DAC circuit. The method 1400begins with providing a load network (e.g., 222 of FIG. 2A) (1410). Themethod further includes providing first set of resistive DAC drivercircuits (e.g., 210 of FIG. 2A) (1420). A first mixing core may beformed by coupling a first input differential pair (e.g., 220 of FIG.2A) to two first cross-coupled differential pairs (e.g., 230 of FIG. 2A)(1430). The first mixing core can receive first RF input signals (e.g.,RF+and RF− of FIG. 2A) from the first set of resistive DAC drivercircuits, and to provide a first mixed signal to the load network(1440). The first input differential pair can receive, at respectivefirst input nodes (e.g., gate node of T1 and T2 of FIG. 2A), first RFinput signals (1450). Each of the two first cross-coupled differentialpairs can receive, at corresponding first input nodes (e.g., gate nodesof T3 and T6 of FIG. 2A), first positive and negative local oscillator(LO) signals (e.g., LO+ and LO− of FIG. 2A) (1460). The first mixingcore can mix the first RF input signals with the first positive andnegative LO signals (1470).

Various examples of aspects of the disclosure are described below asclauses for convenience. These are provided as examples, and do notlimit the subject technology.

Clause A: A double-balanced radio-frequency (RF) mixingdigital-to-analog converter (DAC) apparatus includes a load network, afirst set of resistive DAC driver circuits and a first mixing core. Thefirst mixing core can receive first RF input signals from the first setof resistive DAC driver circuits and can provide a first mixed signal tothe load network. The first mixing core includes a first inputdifferential pair coupled to two first cross-coupled differential pairs.The first input differential pair can receive first RF input signals atrespective first input nodes. Each of the two first cross-coupleddifferential pairs can receive first positive and negative localoscillator (LO) signals at corresponding first input nodes. The firstmixing core can mix the first RF input signals with the first positiveand negative LO signals.

Clause B: A method of providing a double-balanced RF mixing DAC includesproviding a load network and a first set of resistive DAC drivercircuits. The method further includes forming a first mixing core bycoupling a first input differential pair to two first cross-coupleddifferential pairs. The first mixing core can receive first RF inputsignals from the first set of resistive DAC driver circuits and toprovide a first mixed signal to the load network. The first inputdifferential pair can receive, at respective first input nodes, first RFinput signals. Each of the two first cross-coupled differential pairscan receive, at corresponding first input nodes, first positive andnegative local oscillator (LO) signals. The first mixing core can mixthe first RF input signals with the first positive and negative LOsignals.

Clause C: A current-steering RF mixing DAC apparatus includes a loadnetwork, a first set of current-steering DAC driver circuits and asecond set of current-steering DAC driver circuits. The apparatusfurther includes a first mixing core that can receive first RF inputsignals from the first set of current-steering DAC driver circuits andcan provide a first mixed signal to the load network. A second mixingcore can receive second RF input signals from the second set ofcurrent-steering DAC driver circuits and can provide a second mixedsignal to the load network. Each of the first set of current-steeringDAC driver circuits and the second set of current-steering DAC drivercircuits has N input differential pairs. Each input differential pair ofthe N input differential pairs is coupled to a tail transistor. Theinput differential pair is configured to receive, at two correspondinginput nodes, a bit and a respective compliment bit of a first or asecond digital signal. The first set of current-steering DAC drivercircuits can convert the first digital signal to the first RF signal.The second set of current-steering DAC driver circuits can convert thesecond digital signal to the second RF signal. A method comprising oneor more methods, operations or portions thereof described herein.

An apparatus comprising means adapted for performing one or moremethods, operations or portions thereof described herein.

A hardware apparatus comprising circuits configured to perform one ormore methods, operations or portions thereof described herein.

An apparatus comprising means adapted for performing one or moremethods, operations or portions thereof described herein.

An apparatus comprising components operable to carry out one or moremethods, operations or portions thereof described herein.

In one aspect, a method may be an operation, an instruction, or afunction and vice versa. In one aspect, a clause may be amended toinclude some or all of the words (e.g., instructions, operations,functions, or components) recited in other one or more clauses, one ormore words, one or more sentences, one or more phrases, one or moreparagraphs, and/or one or more claims. During prosecution, one or moreclaims may be amended to depend on one or more other claims, and one ormore claims may be amended to delete one or more limitations.

A reference to an element in the singular is not intended to mean oneand only one unless specifically so stated, but rather one or more. Forexample, “a” module may refer to one or more modules. An elementproceeded by “a,” “an,” “the,” or “said” does not, without furtherconstraints, preclude the existence of additional same elements.

Headings and subheadings, if any, are used for convenience only and donot limit the invention. The word exemplary is used to mean serving asan example or illustration. To the extent that the term include, have,or the like is used, such term is intended to be inclusive in a mannersimilar to the term comprise as comprise is interpreted when employed asa transitional word in a claim. Relational terms such as first andsecond and the like may be used to distinguish one entity or action fromanother without necessarily requiring or implying any actual suchrelationship or order between such entities or actions.

Phrases such as an aspect, the aspect, another aspect, some aspects, oneor more aspects, an implementation, the implementation, anotherimplementation, some implementations, one or more implementations, anembodiment, the embodiment, another embodiment, some embodiments, one ormore embodiments, a configuration, the configuration, anotherconfiguration, some configurations, one or more configurations, thesubject technology, the disclosure, the present disclosure, othervariations thereof and alike are for convenience and do not imply that adisclosure relating to such phrase(s) is essential to the subjecttechnology or that such disclosure applies to all configurations of thesubject technology. A disclosure relating to such phrase(s) may apply toall configurations, or one or more configurations. A disclosure relatingto such phrase(s) may provide one or more examples. A phrase such as anaspect or some aspects may refer to one or more aspects and vice versa,and this applies similarly to other foregoing phrases.

A phrase “at least one of” preceding a series of items, with the terms“and” or “or” to separate any of the items, modifies the list as awhole, rather than each member of the list. The phrase “at least one of”does not require selection of at least one item; rather, the phraseallows a meaning that includes at least one of any one of the items,and/or at least one of any combination of the items, and/or at least oneof each of the items. By way of example, each of the phrases “at leastone of A, B, and C” or “at least one of A, B, or C” refers to only A,only B, or only C; any combination of A, B, and C; and/or at least oneof each of A, B, and C.

In one aspect, a transistor may be a bipolar junction transistor (BJT),and it may refer to any of a variety of multi-terminal transistorsgenerally operating on the principal of carrying current using bothelectrons and holes, including but not limited to an n-p-n BJT and ap-n-p BJT.

In one aspect, a transistor may be a field effect transistor (FET), andit may refer to any of a variety of multi-terminal transistors generallyoperating on the principals of controlling an electric field to controlthe shape and hence the conductivity of a channel of one type of chargecarrier in a semiconductor material, including, but not limited to ametal oxide semiconductor field effect transistor (MOSFET), a junctionFET (JFET), a metal semiconductor FET (MESFET), a high electron mobilitytransistor (HEMT), a modulation doped FET (MODFET), an insulated gatebipolar transistor (IGBT), a fast reverse epitaxial diode FET (FREDFET),and an ion-sensitive FET (ISFET).

In one aspect, the terms base, emitter, and collector may refer to threeterminals of a transistor and may refer to a base, an emitter and acollector of a bipolar junction transistor or may refer to a gate, asource, and a drain of a field effect transistor, respectively, and viceversa. In another aspect, the terms gate, source, and drain may refer tobase, emitter, and collector of a transistor, respectively, and viceversa.

Unless otherwise mentioned, various configurations described in thepresent disclosure may be implemented on a Silicon, Silicon-Germanium(SiGe), Gallium Arsenide (GaAs), Indium Phosphide (InP) or IndiumGallium Phosphide (InGaP) substrate, or any other suitable substrate.

It is understood that the specific order or hierarchy of steps,operations, or processes disclosed is an illustration of exemplaryapproaches. Unless explicitly stated otherwise, it is understood thatthe specific order or hierarchy of steps, operations, or processes maybe performed in different order. Some of the steps, operations, orprocesses may be performed simultaneously. The accompanying methodclaims, if any, present elements of the various steps, operations orprocesses in a sample order, and are not meant to be limited to thespecific order or hierarchy presented. These may be performed in serial,linearly, in parallel or in different order.

In one aspect, a term coupled or the like may refer to being directlycoupled. In another aspect, a term coupled or the like may refer tobeing indirectly coupled.

Terms such as top, bottom, front, rear, side, horizontal, vertical, andthe like refer to an arbitrary frame of reference, rather than to theordinary gravitational frame of reference. Thus, such a term may extendupwardly, downwardly, diagonally, or horizontally in a gravitationalframe of reference.

The disclosure is provided to enable any person skilled in the art topractice the various aspects described herein. In some instances,well-known structures and components are shown in block diagram form inorder to avoid obscuring the concepts of the subject technology. Thedisclosure provides various examples of the subject technology, and thesubject technology is not limited to these examples. Variousmodifications to these aspects will be readily apparent to those skilledin the art, and the principles described herein may be applied to otheraspects.

All structural and functional equivalents to the elements of the variousaspects described throughout the disclosure that are known or later cometo be known to those of ordinary skill in the art are expresslyincorporated herein by reference and are intended to be encompassed bythe claims. Moreover, nothing disclosed herein is intended to bededicated to the public regardless of whether such disclosure isexplicitly recited in the claims. No claim element is to be construedunder the provisions of 35 U.S.C. § 112, sixth paragraph, unless theelement is expressly recited using the phrase “means for” or, in thecase of a method claim, the element is recited using the phrase “stepfor”.

The title, background, brief description of the drawings, abstract, anddrawings are hereby incorporated into the disclosure and are provided asillustrative examples of the disclosure, not as restrictivedescriptions. It is submitted with the understanding that they will notbe used to limit the scope or meaning of the claims. In addition, in thedetailed description, it can be seen that the description providesillustrative examples and the various features are grouped together invarious implementations for the purpose of streamlining the disclosure.The method of disclosure is not to be interpreted as reflecting anintention that the claimed subject matter requires more features thanare expressly recited in each claim. Rather, as the claims reflect,inventive subject matter lies in less than all features of a singledisclosed configuration or operation. The claims are hereby incorporatedinto the detailed description, with each claim standing on its own as aseparately claimed subject matter.

The claims are not intended to be limited to the aspects describedherein, but are to be accorded the full scope consistent with thelanguage claims and to encompass all legal equivalents. Notwithstanding,none of the claims are intended to embrace subject matter that fails tosatisfy the requirements of the applicable patent law, nor should theybe interpreted in such a way.

What is claimed is:
 1. A double-balanced radio frequency (RF) mixingdigital-to-analog converter (DAC) apparatus, the apparatus comprising: aload network; a first set of resistive DAC driver circuits; and a firstmixing core configured to receive first RF input signals from the firstset of resistive DAC driver circuits and to provide a first mixed signalto the load network, wherein: the first mixing core comprises a firstinput differential pair coupled to two first cross-coupled differentialpairs, the first input differential pair is configured to receive firstRF input signals at respective first input nodes, each of the two firstcross-coupled differential pairs is configured to receive first positiveand negative local oscillator (LO) signals at corresponding first inputnodes, and the first mixing core is configured to mix the first RF inputsignals with the first positive and negative LO signals.
 2. Theapparatus of claim 1, further comprising a tail current source coupledto a common node of the first input differential pair.
 3. The apparatusof claim 1, wherein the first input differential pair and the two firstcross-coupled differential pairs comprise metal-oxide semiconductor(MOS) transistors, and wherein MOS transistors comprise NMOStransistors.
 4. The apparatus of claim 3, wherein the load networkcomprises two resistors coupled to a voltage bias source at a commonfirst node of the two resistors, and wherein second nodes of the tworesistors are coupled to first output nodes of the two firstcross-coupled differential pairs.
 5. The apparatus of any of claims 4,further comprising: a second set of resistive DAC driver circuits; and asecond mixing core configured to receive second RF input signals fromthe second set of resistive DAC driver circuits and to provide a secondmixed signal to the load network, wherein: the second mixing corecomprises a second input differential pair coupled to two secondcross-coupled differential pairs, the second input differential pair isconfigured to receive second RF input signals at respective second inputnodes, each of the two second cross-coupled differential pairs isconfigured to receive second positive and negative local oscillator (LO)signals at corresponding second input nodes, and the second mixing coreis configured to mix the second RF input signals with the secondpositive and negative LO signals.
 6. The apparatus of claim 1, whereinthe apparatus is configured as a fold-back circuit, and wherein in thefold-back circuit the first input differential pair comprises: a firstset of PMOS transistors; gate nodes of the first set of PMOS transistorsare coupled to the first set of resistive DAC driver circuits; drainnodes of the first set of PMOS transistors are coupled the load network;and source nodes of the first set of PMOS transistors are coupled to afirst set of bias current sources.
 7. The apparatus of claim 6, wherein:transistors of the first mixing core comprise NMOS transistors, commonsource nodes of the two first cross-coupled differential pairs arecoupled via a first pair of tail transistors to a ground potential; andcommon drain nodes of the two first cross-coupled differential pairs arecoupled to the source nodes of the first set of PMOS transistors.
 8. Theapparatus of claim 6, wherein the apparatus is configured as a fold-backcircuit, and wherein in the fold-back circuit the first inputdifferential pair comprises: a second set of PMOS transistors; gatenodes of the second set of PMOS transistors are coupled to a second setof resistive DAC driver circuits; drain nodes of the second set of PMOStransistors are coupled the load network; and source nodes of the secondset of PMOS transistors are coupled to a second set of bias currentsources.
 9. The apparatus of claim 8, further comprising a second mixingcore comprising a second set of cross-coupled differential pairs formedof NMOS transistors, wherein: common source nodes of the two secondcross-coupled differential pairs are coupled via a second pair of tailtransistors to a ground potential, and common drain nodes of the twosecond cross-coupled differential pairs are coupled to the source nodesof the second set of PMOS transistors.
 10. A current-steeringradio-frequency (RF) mixing digital-to-analog converter (DAC) apparatus,the apparatus comprising: a load network; a first set ofcurrent-steering DAC driver circuits; a second set of current-steeringDAC driver circuits; a first mixing core configured to receive first RFinput signals from the first set of current-steering DAC driver circuitsand to provide a first mixed signal to the load network; and a secondmixing core configured to receive second RF input signals from thesecond set of current-steering DAC driver circuits and to provide asecond mixed signal to the load network, wherein: each of the first setof current-steering DAC driver circuits and the second set ofcurrent-steering DAC driver circuits comprises N input differentialpairs, each input differential pair of the N input differential pairs iscoupled to a tail transistor, the input differential pair is configuredto receive, at two corresponding input nodes, a bit and a respectivecompliment bit of a first or a second digital signal, the first set ofcurrent-steering DAC driver circuits are configured to convert the firstdigital signal to the first RF signal, and the second set ofcurrent-steering DAC driver circuits are configured to convert thesecond digital signal to the second RF signal.
 11. The apparatus ofclaim 10, wherein: the first mixing core comprises first cross-coupleddifferential pairs configured to receive in-phase (I) positive andnegative LO signals at corresponding first input nodes, and the secondmixing core comprises second cross-coupled differential pairs configuredto receive quadrature positive and negative local oscillator (LO)signals at corresponding first input nodes.
 12. The apparatus of claim10, wherein: each of the first mixing core and the second mixing corecomprises a first differential pair coupled in parallel with a seconddifferential pair, the first differential pair is configured to receivepositive LO signals and to provide first output currents, and the seconddifferential pair is configured to receive negative LO signals and toprovide dump currents for the first set of current-steering DAC drivercircuits when transistors of the first differential pair are off
 13. Theapparatus of claim 12, wherein: the first differential pair is coupledto the load network and is configured to provide output currents to theload network, and the second differential pair is coupled to a dumpcurrent source configured to provide the dump currents.
 14. Theapparatus of claim 12, further comprising a T-coil network, and whereinthe first differential pair is coupled to a T-coil network, and whereinthe T-coil network is coupled to the load network.
 15. The apparatus ofclaim 14, further comprising a power combiner configured to couple theT-coil network to an output circuit.
 16. A method of providing adouble-balanced radio-frequency (RF) mixing digital-to-analog converter(DAC), the method comprising: providing a load network; providing afirst set of resistive DAC driver circuits; forming a first mixing coreby coupling a first input differential pair to two first cross-coupleddifferential pairs; configuring the first mixing core to receive firstRF input signals from the first set of resistive DAC driver circuits andto provide a first mixed signal to the load network; configuring thefirst input differential pair to receive, at respective first inputnodes, first RF input signals; configuring each of the two firstcross-coupled differential pairs to receive, at corresponding firstinput nodes, first positive and negative local oscillator (LO) signals;and configuring the first mixing core to mix the first RF input signalswith the first positive and negative LO signals.
 17. The method of claim16, further comprising: providing a second set of resistive DAC drivercircuits; forming a second mixing core by coupling a second inputdifferential pair to two second cross-coupled differential pairs;configuring the second mixing core to receive second RF input signalsfrom the second set of resistive DAC driver circuits and to provide asecond mixed signal to the load network; configuring the second inputdifferential pair to receive, at respective second input nodes, secondRF input signals; configuring each of the two second cross-coupleddifferential pairs to receive, at corresponding second input nodes,second positive and negative local oscillator (LO) signals; andconfiguring the second mixing core to mix the second RF input signalswith the second positive and negative LO signals.
 18. The method ofclaim 16, further comprising configuring a fold-back circuit and in thefold-back circuit forming the first input differential pair by:providing a first set of PMOS transistors; coupling gate nodes of thefirst set of PMOS transistors to the first set of resistive DAC drivercircuits; coupling drain nodes of the first set of PMOS transistors tothe load network; and coupling source nodes of the first set of PMOStransistors to a first set of bias current sources.
 19. The method ofclaim 18, further comprising forming, using NMOS transistors, a secondmixing core using a second set of cross-coupled differential pairs. 20.The method of claim 19, wherein forming the second mixing corecomprises: coupling common source nodes of the two second cross-coupleddifferential pairs via a second pair of tail transistors to a groundpotential; and coupling common drain nodes of the two secondcross-coupled differential pairs to the source nodes of a second set ofPMOS transistors.